Method for fabricating low leakage interconnect layers in integrated circuits

ABSTRACT

A method for fabricating a low leakage integrated circuit structure. An antireflective layer is disposed without intervening layers directly onto the top of an interconnect conductor, and a dielectric layer is disposed over the antireflective layer. The interconnect conductor is aluminum; the antireflective layer is titanium nitride, and the antireflective layer has thickness less than or equal to 650 angstroms and greater than or equal to 150 angstroms. A contact window is opened with the contact window extending at least down to the antireflective layer.

BACKGROUND

Most advanced integrated circuit (IC) processes having 0.35 micron orsmaller geometries include an antireflective (AR) coating on top of eachmetallization layer to improve the lithography process margin inpatterning smaller features in the integrated circuit. Suchantireflective coating reduces exposure dispersion of the interconnectlayer photoresist, thus providing a sharper image pattern which improvesthe definition of interconnect features. Typically for aluminum/tungsten(Al/W) based metallization systems, a flash titanium layer (flash Ti) isapplied between the aluminum (Al) and the antireflective layer which isgenerally titanium nitride (TiN). Tungsten is used to fill the vias thatinterconnect the layers of aluminum. The flash titanium layer is alsoreferred to as a titanium initiation layer. The flash titanium layer isnecessary to prevent a broad distribution of contact resistance whichwould otherwise result from the formation of aluminum nitride (AlN)during the deposition of the top antireflective titanium nitride, aswell as during subsequent exposure to nitrogen plasma during resist ashsteps.

Without the flash titanium layer, a few regions of aluminum nitridewould be created on top of the aluminum due to the introduction ofnitrogen gas into the sputtering chamber during the deposition of thetop antireflective titanium nitride onto the aluminum. If the aluminumnitride layer regions happen to be at the bottom of a contact, then suchcontacts would have higher contact resistance resulting in a broaddistribution of contact resistance to the next interconnect layer.

The flash layer of titanium and the antireflective coating of titaniumnitride are generally deposited using the same sputtering chamber.Titanium is sputtered from a titanium target in the chamber during thefirst part of the process. Then the antireflective coating of titaniumnitride is deposited on the wafers in the same chamber by introducingthe nitrogen into the chamber after a set delay following the onset oftitanium sputtering.

During subsequent thermal processing, it is anticipated that thistitanium will react with the aluminum to form titanium aluminide (TiAl₃)which will prevent hydrogen gettering by this layer of titanium.However, due to the normal practice of depositing the layer of flashtitanium in most integrated circuit processes, an unintentional layer oftitanium nitride is deposited between the aluminum and the titanium.This extra, unintentional layer of titanium nitride inhibits thereaction of the titanium layer with the aluminum during subsequentthermal processing unless the temperature and temperature duration (thethermal budget) of subsequent processing steps is very high. In mostintegrated circuit processes, the thermal budget of steps subsequent toaluminum deposition is not sufficient to overcome the barrier presentedby the unintentional layer of titanium nitride.

Thus, a result of the failure to overcome the barrier of theunintentional layer of titanium nitride is the gettering of hydrogen bythe titanium layer. Hydrogen gettering by the titanium layer results ininsufficient passivation of dangling bonds at the silicon/silicondioxide interface which leads to higher leakage currents in suchintegrated circuits. Depending upon the specific spatial distribution ofthe metallization in the integrated circuit, these dangling bonds at thesilicon/oxide interface can lead to larger leakage currents with morevariability across large area arrays as are commonly found in CMOS Imagesensors.

Leakage current for a light sensitive element, for example as found in apixel of an image sensor, is often referred to as the dark current ofthe device, i.e., the current through the light sensitive element in theabsence of any light. The lowest light intensity that is detectable bythe device is dictated by the noise in the device and the dark current.Thus, it is important to maintain the leakage currents as small aspossible, as well as to maintain a uniformity in the magnitudes of theleakage currents across the image sensor.

SUMMARY

In a representative embodiment, a method for fabricating a low leakageintegrated circuit structure is disclosed. The method comprisesdisposing an antireflective layer without intervening layers directlyonto the top of an interconnect conductor and disposing a dielectriclayer over the antireflective layer. The interconnect conductor isaluminum; the antireflective layer is titanium nitride, and theantireflective layer has thickness less than or equal to 650 angstromsand greater than or equal to 150 angstroms. A contact window is openedwith the contact window extending at least down to the antireflectivelayer.

In another representative embodiment, an integrated circuit structure isdisclosed. The integrated circuit structure comprises an interconnectconductor disposed over other integrated circuit structure, anantireflective layer disposed without intervening layers directly ontothe top of the interconnect conductor, and a dielectric layer disposedover the antireflective layer. The interconnect conductor comprisesaluminum, and the antireflective layer comprises titanium nitride. Theantireflective layer has thickness less than or equal to 650 angstromsand greater than or equal to 150 angstroms. The dielectric layercomprises a contact window with the contact window extending at leastdown to the antireflective layer.

In yet another representative embodiment, a method for fabricating a lowleakage integrated circuit structure is disclosed. The method comprisesplacing the integrated circuit structure in a deposition chamber,disposing a flash titanium layer without intervening layers directlyonto the top of the interconnect conductor, and disposing anantireflective layer over the flash titanium layer. The integratedcircuit structure has an interconnect conductor disposed thereon. Theinterconnect conductor comprises aluminum, and the antireflective layercomprises titanium nitride. The above steps are then repeated for atleast one additional integrated circuit structure.

Other aspects and advantages of the representative embodiments presentedherein will become apparent from the following detailed description,taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings provide visual representations which will beused to more fully describe various representative embodiments and canbe used by those skilled in the art to better understand them and theirinherent advantages. In these drawings, like reference numerals identifycorresponding elements.

FIG. 1A is a drawing of a cross-section of a part of an integratedcircuit structure as described in various representative embodiments.

FIG. 1B is a drawing of a cross-section of another integrated circuitstructure as described in various representative embodiments.

FIG. 2 is a drawing of a cross-section of still another integratedcircuit structure as described in various representative embodiments.

FIG. 3 is a drawing of a cross-section of yet another integrated circuitstructure as described in various representative embodiments.

FIG. 4A is a drawing of a cross-section of an integrated circuit topinterconnect layer as described in various representative embodiments.

FIG. 4B is a drawing of a cross-section of an integrated circuitunderlying interconnect layer as described in various representativeembodiments.

FIG. 4C is a drawing of a cross-section of an integrated circuitstructure having the integrated circuit underlying interconnect layer ofFIG. 4B.

FIG. 4D is a flow chart of a method for creating an integrated circuitstructure having the integrated circuit underlying interconnect layer ofFIG. 4B.

FIG. 5A is a drawing of a deposition chamber as described in variousrepresentative embodiments.

FIG. 5B is a drawing of another deposition chamber as described invarious representative embodiments.

FIG. 5C is a flow chart of a method for creating an integrated circuitstructure using the two deposition chambers of FIGS. 5A and 5B.

FIG. 5D is a flow chart of a method for creating an integrated circuitstructure using pasting as described in various representativeembodiments.

FIG. 6A is a drawing of still another deposition chamber as described invarious representative embodiments.

FIG. 6B is a flow chart of a method for creating an integrated circuitstructure using a shield as described in various representativeembodiments.

FIG. 7A is a drawing of a cross-section of even still another integratedcircuit structure as described in various representative embodiments.

FIG. 7B is a flow chart of a method for creating an integrated circuitstructure using a thin antireflective coating as described in variousrepresentative embodiments.

FIG. 8 is a flow chart of a method for creating an integrated circuitstructure using lower temperature tungsten deposition as described invarious representative embodiments.

DETAILED DESCRIPTION

As shown in the drawings for purposes of illustration, novel techniqueswhich can be integrated into existing integrated circuit (IC) processesthat use aluminum/tungsten (Al/W) based metallization systems aredisclosed herein. These techniques enable maintaining small values ofleakage currents while controlling the variability of contactresistances and leakage currents over large area arrays. The leakagecurrents of interest typically comprise p-n junction diode leakage.

An antireflective (AR) coating included on top of the interconnection(metallization) layers for most advanced integrated circuit processeshaving 0.35 micron or smaller geometries improves the lithographyprocess margin in patterning smaller features in the integrated circuit.The inclusion of this antireflective coating reduces pattern dispersionduring exposure of the interconnect layer photoresist, thereby producinga sharper image pattern resulting in improved definition of interconnectfeatures. Typically for aluminum/tungsten based metallization systems, aflash titanium layer (flash Ti) is applied between the aluminum (Al) andthe antireflective layer. This antireflective coating is generallytitanium nitride (TiN). Tungsten (W) is used to fill the vias thatinterconnect the layers of aluminum. The flash titanium layer generallyprevents a broad distribution of contact resistance which wouldotherwise result from the formation of aluminum nitride (AlN) during thedeposition of the top antireflective titanium nitride and subsequentexposure of the wafer to nitrogen plasma during resist ash steps.

It is important that the titanium be consumed by the underlying layer ofaluminum during the subsequent thermal processing. As the consumption ofthe titanium by the aluminum is inhibited by the unintentional titaniumnitride layer, there is a need to eliminate or reduce the effect of thisunintentional titanium nitride layer. In the following detaileddescription and in the several figures of the drawings, like elementsare identified with like reference numerals.

FIG. 1A is a drawing of a cross-section of part of an integrated circuitstructure 100 as described in various representative embodiments. InFIG. 1A, the part of the integrated circuit structure 100 comprises aninterconnect conductor 110, also referred to herein as an interconnectlayer 110, an initiation layer 120, and an antireflective layer 130. Theinitiation layer 120 lies on top of the interconnect conductor 110, andthe antireflective layer 130 lies on top of the initiation layer 120. Inthis representative example of FIG. 1A, the interconnect conductor 110is aluminum and as such is referred to as aluminum layer 110, and theinitiation layer 120 is also referred to as flash titanium layer 120. Inthe representative example of FIG. 1A, the antireflective layer 130 istitanium nitride. FIG. 1A and other drawings herein are for illustrativepurposes only and are not drawn to scale.

For processes in which the interconnect conductor 110 is aluminum, theinitiation layer 120 is titanium, and the antireflective layer 130 istitanium nitride. In which case, the flash titanium layer 120 and theantireflective layer 130 are typically deposited one after the other inthe same chamber. Starting from a clean titanium target, the first waferreceives a cleanly sputtered layer of titanium, the initiation layer 120which is referred to as the flash titanium layer 120 or the titaniuminitiation layer 120. Nitrogen gas is then turned on in the chamberwhile titanium sputtering continues resulting in the deposition oftitanium nitride on the wafer. The result of this process for the firstwafer is shown in FIG. 1A.

FIG. 1B is a drawing of a cross-section of another integrated circuitstructure 100 as described in various representative embodiments. In therepresentative embodiment of FIG. 1B, the part of the integrated circuitstructure 100 comprises the interconnect conductor 110, an inhibitinglayer 140, the initiation layer 120, and the antireflective layer 130.The inhibiting layer 140 lies on top of the interconnect conductor 110,the initiation layer 120 lies on top of the inhibiting layer 140, andthe antireflective layer 130 lies on top of the initiation layer 120. Inthis representative example of FIG. 1B, the interconnect conductor 110is aluminum, the initiation layer 120 is flash titanium, the inhibitinglayer 140 is unintentional titanium nitride which is then referred to asunintentional titanium nitride layer 140, and the antireflective layer130 is titanium nitride.

At the same time that titanium nitride is being deposited onto thewafer, titanium nitride is also being formed on the titanium target. Assuch, during subsequent wafer processing, instead of initiallysputtering titanium from the titanium target, titanium nitride isinitially sputtered followed by titanium once the titanium nitrideformed on the target from the previous wafer processing has beenremoved. Thus, subsequent to the first wafer processed in the chamberwith a clean target, the wafers will first receive an unintentionallayer of titanium nitride and then a layer of titanium before thenitrogen gas is turned on. This layer of titanium nitride is a fewatomic layers thick and is not very uniform in thickness across the topof the aluminum. The result of this process for wafers subsequent to thefirst wafer is shown in FIG. 1B. Due to the non-uniformity and thinnessof the unintentional titanium nitride layer 140, it will have locationsin which holes 141 in the film exist. As such, the flash titanium layer120 and the aluminum layer 110 will be in contact at boundaries 142.

FIG. 2 is a drawing of a cross-section of still another integratedcircuit structure 100 as described in various representativeembodiments. In the representative embodiment of FIG. 2, the initialsteps used to construct or fabricate the integrated circuit structure100 are the same as those used to fabricate the integrated circuitmetallization structure 100 of FIG. 1A. Following the construction ofthe integrated circuit structure 100 of FIG. 1A which includes theinitiation layer 120 and the antireflective layer 130 on top of theinterconnect conductor 110, the flash titanium layer 120 is reacted withthe aluminum layer 110 to create reacted layer 210 which in therepresentative embodiment of FIG. 2 is titanium aluminide (TiAl₃) layer210. Again, this structure would be the result of processing the firstwafer in the titanium sputtering chamber. Following these processingsteps and after a contact window 710 has been opened in dielectric layer220 disposed over the antireflective layer 130 and shown in FIG. 2 asSiO₂ layer 220, a seed titanium layer 230, a seed titanium nitride layer240, and a tungsten plug layer 250 are sequentially deposited to form aninterconnection through the contact window 710 or via 710 to the nextinterconnect layer 110. Prior to the formation of this interconnection,however, the wafer receives a tungsten polish. The tungsten polish istypically a chemical mechanical polish which removes those parts of thetungsten plug layer 250, the seed titanium nitride layer 240, and theseed titanium layer 230 that overlie the dielectric layer 220. Theintegrated circuit structure 100 is then as shown in FIG. 2 withessentially the only remaining tungsten from the tungsten plug layer 250residing in the contact window 710. That remaining part of the tungstenplug layer 250 is now referred to as the tungsten plug 250.

The purpose of the seed titanium layer 230 is to getter any oxide fromthe top of the aluminum layer 110 at the bottom of the contact via so asto make a good electrical contact to the aluminum layer 110. The seedtitanium layer 230 also aids in providing good adhesion between thetungsten plug 250 and dielectric layer 220 exposed on the sidewall ofthe contact via as tungsten does not adhere well to silicon dioxide.

The purpose of the seed titanium nitride layer 240 is to protect theseed titanium layer 230 from attack by processing components duringtungsten plug 250 deposition. The seed titanium nitride layer 240 alsoprovides electrical contact between the titanium nitride layer 240 andthe tungsten plug 250.

FIG. 3 is a drawing of a cross-section of yet another integrated circuitstructure 100 as described in various representative embodiments. In therepresentative embodiment of FIG. 3, the initial steps used to constructor fabricate the integrated circuit structure 100 are the same as thoseused to fabricate the integrated circuit structure 100 of FIG. 1B.Following the construction of the integrated circuit structure 100 ofFIG. 1B, subsequent processing intended to react the flash titaniumlayer 120 with the aluminum layer 110 to create a reacted layer 210 asthe titanium aluminide (TiAl₃) layer 210 of FIG. 2 is, however,inhibited by the unintentional titanium nitride layer 140 in thoselocations where it is sufficiently thick. In other locations where theunintentional titanium is not thick enough, it will react with thealuminum to form titanium aluminide.

As discussed with respect to FIG. 1B, the unintentional titanium nitridelayer 140 is only a few atomic layers thick and non-uniform in thicknessacross the top surface of the aluminum layer 110. Due to thenon-uniformity and thinness of the unintentional titanium nitride layer140, it will have locations in which holes 141 in the film exist. Assuch, the flash titanium layer 120 and the aluminum layer 110 will be incontact at boundaries 142. At these boundaries 142, subsequentprocessing reacts the titanium in the flash titanium layer 120 with thealuminum in the aluminum layer 110 to create the titanium aluminidelayer 210 which is also non-uniform in extent and thickness across thetop surface of the aluminum layer 110. It is effectively in thoselocations where holes 141 exist in the unintentional titanium nitridelayer 140 that titanium from the flash titanium layer 120 can react withthe aluminum in the interconnect conductor 110 to tie up the freetitanium in the flash titanium layer 120 thereby forming titaniumaluminide.

Following these processing steps and after a contact window 710 has beenopened in the dielectric layer 220 disposed over the antireflectivelayer 130 and shown in FIG. 3 as SiO₂ layer 220, the seed titanium layer230, the seed titanium nitride layer 240, and the tungsten plug layer250 are sequentially deposited to form an interconnection through thecontact window 710 or via 710 to the next interconnect layer 110. Priorto the formation of this interconnection, however, the wafer receives atungsten polish. The tungsten polish is again typically a chemicalmechanical polish which removes those parts of the tungsten plug layer250, the seed titanium nitride layer 240, and the seed titanium layer230 that overlie the dielectric layer 220. The integrated circuitstructure 100 is then as shown in FIG. 3 with essentially the onlyremaining tungsten from the tungsten plug layer 250 residing in thecontact window 710. Once again, that remaining part of the tungsten pluglayer 250 is now referred to as the tungsten plug 250.

The presence of the unintentional titanium nitride layer 140 results inincreased gettering of hydrogen from the SiO₂ layer 220 by the unreactedflash titanium layer 120. The hydrogen gettered from the surroundingoxides and other layers creates a concentration gradient of hydrogendown to the silicon (Si) diode surface. This gettering pulls hydrogenthat otherwise would have satisfied dangling bonds at thesilicon/silicon dioxide interface. As such, an increased number ofinterface states are left at that interface resulting in an increase inleakage current.

So, in order to reduce leakage currents, it is important to keephydrogen attached to these dangling bonds. Forming titanium aluminideties up the free titanium thereby preventing it from gettering hydrogenwhich would otherwise result in a higher defect density at thesilicon/silicon-dioxide interface. Again, the cause of thesedifficulties is due to the fact that the flash titanium layer 120 istypically deposited in the same chamber as the antireflective layer 130is deposited which results in the unintentional titanium nitride layer140 interposed between the aluminum layer 110 and the flash titaniumlayer 120. Subsequent thermal steps are typically unable to convert allof the titanium in the flash titanium layer 120 with aluminum from thealuminum layer 110 to form titanium aluminide due to the presence of theunintentional titanium nitride layer 140. Any remaining free titaniumcan then getter hydrogen from the surrounding oxides resulting inleakage currents that are greater than would have otherwise existed hadall the titanium been converted into titanium aluminide.

FIG. 4A is a drawing of a cross-section of an integrated circuit topinterconnect layer 400 as described in various representativeembodiments. In the example of FIG. 4A, the integrated circuit topinterconnect layer 400 comprises the aluminum layer 110 and theantireflective layer 130, but not the flash titanium layer 120. As theflash titanium layer 120 is absent, so also is the unintentionaltitanium nitride layer 140. Since this is the top interconnect layer110, by default there is not a tungsten plug 250 on top of this layerand no contacts are made to this layer from above. Thus, there is not anissue with increased contact resistance or large variations in contactresistance across the wafer even though aluminum nitride is formedduring deposition of the antireflective layer 130 and subsequentexposure of the wafer to nitrogen plasma during resist ash steps. Inaddition, normally the aluminum and titanium react during subsequenttungsten plug 250 deposition or subsequent high temperature thermalsteps. But, for the final, top interconnect layer 100 there is nosubsequent plug deposition and typically only one subsequent hightemperature step is left in the process flow. This final hightemperature step is the final anneal. Final anneal generally occurs in atemperature range of 390-420 degrees centigrade. As such, final annealis typically insufficient to completely react the titanium with thealuminum. Thus, removal of the flash titanium step for the topinterconnect layer does not present additional problems as the situationis not made worse with respect to the gettering of hydrogen with theassociated increase in leakage current since free titanium is notpresent to provide such gettering.

FIG. 4B is a drawing of a cross-section of an integrated circuitunderlying interconnect layer 410 as described in various representativeembodiments. In the representative embodiment of FIG. 4B, the integratedcircuit underlying interconnect layer 410 comprises the interconnectconductor (aluminum layer) 110 and the antireflective layer 130, but notthe flash titanium layer 120. The antireflective layer 130 is typicallybetween 150 and 650 angstroms thick. As the flash titanium layer 120 isabsent, so also is the unintentional titanium nitride layer 140.However, for the underlying interconnect layers 410 the flash titaniumlayer 120 cannot just be eliminated as this would result in a broaddistribution of contact resistance due to the presence of aluminumnitride at the bottom of the contact. In order to get around this issue,the contact etch is stopped at the top of the thicker (typically 350 to650 angstroms) antireflective layer 130, i.e., the top of the titaniumnitride. This is achieved by using an etch chemistry that has a highselectivity, i.e., the etch rate of oxide is significantly larger thanthe etch rate of titanium nitride. In this scheme, the flash titaniumlayer 120 is eliminated. The thicker remaining titanium nitride aftercontact etch also ensures that there is no further aluminum nitrideformation during subsequent processing steps. While the contactresistance will increase due to the presence of titanium nitride at thebottom of the contact, it does so uniformly across the wafer. Further,since the flash titanium layer 120 is eliminated, there is no remainingfree titanium on top of the aluminum layer 110 to getter hydrogen. Thereis a sufficiently broad contact area to negate the effect of theformation of aluminum nitride in some places.

FIG. 4C is a drawing of a cross-section of an integrated circuitstructure 100 having the integrated circuit underlying interconnectlayer 410 of FIG. 4B. In the representative embodiment of FIG. 4C, thecontact etch has been stopped on top of the antireflective layer 130.The initial steps used to construct or fabricate the integrated circuitstructure 100 of FIG. 4C are the same as those used to fabricate theintegrated circuit structure 100 of FIG. 4B. Following the constructionof the integrated circuit structure 100 of FIG. 4B and subsequentprocessing which includes deposing the dielectric layer 220 on top overthe antireflective layer 130, the contact window 710 is opened in thedielectric layer 220 shown in FIG. 4C as SiO₂ layer 220, the seedtitanium layer 230, the seed titanium nitride layer 240, and thetungsten plug layer 250 are sequentially deposited to form aninterconnection through the contact window 710 or via 710 to the nextinterconnect layer 110. Prior to the formation of this interconnection,however, the wafer receives a tungsten polish. The tungsten polish isagain typically a chemical mechanical polish which removes those partsof the tungsten plug layer 250, the seed titanium nitride layer 240, andthe seed titanium layer 230 that overlie the dielectric layer 220. Theintegrated circuit structure 100 is then as shown in FIG. 4C withessentially the only remaining tungsten from the tungsten plug layer 250residing in the contact window 710.. Once again, that remaining part ofthe tungsten plug layer 250 is now referred to as the tungsten plug 250.

Also shown in FIG. 4C are uneven aluminum nitride regions 720 which wereformed during titanium nitride deposition, as well as subsequent resistash steps.

FIG. 4D is a flow chart of a method for creating an integrated circuitstructure 100 having the integrated circuit underlying interconnectlayer 410 of FIG. 4B. In block 1450 of FIG. 4D, the interconnectconductor 110 is deposited on top of other features on the semiconductorsubstrate. Block 1450 then transfers control to block 1455.

In block 1455, the antireflective layer 130 is deposited on top of theinterconnect conductor 110. Block 1450 then transfers control to block1460.

In block 1460, other processing steps are performed including thecreation of the dielectric layer 220. Block 1460 then transfers controlto block 1465.

In block 1465, a contact via, also referred to as a contact window, isetched in the dielectric layer 220 which stops on top of theantireflective layer 130. The contact via is etched using a highselectivity etch for which the silicon dioxide etch rate issignificantly larger than titanium nitride etch rate. Block 1465 thentransfers control to block 1470.

In block 1470, the seed titanium layer 230 is deposited. Block 1470 thentransfers control to block 1475.

In block 1475, the seed titanium nitride layer 240 is deposited. Block1475 then transfers control to block 1480.

In block 1480, the tungsten plug 250 is deposited. Block 1480 thentransfers control to block 1490.

In block 1490, the tungsten, titanium nitride, and titanium in regionsother than the tungsten plug regions are removed by using chemicalmechanical polishing in a process typically referred to as a tungstenpolish. Block 1490 then terminates the process.

FIG. 5A is a drawing of a deposition chamber as described in variousrepresentative embodiments. FIG. 5B is a drawing of another depositionchamber as described in various representative embodiments. Included inFIG. 5A is a first deposition chamber 500, which in representativeembodiments is a flash titanium deposition chamber 500, and included inFIG. 5B is a second deposition chamber 505, which in representativeembodiments is a titanium nitride deposition chamber 505. Both first andsecond deposition chambers 500,505 comprise targets 530 which inrepresentative embodiments are titanium targets 530. The titaniumnitride deposition chamber 505 includes a gas port 550 by which a gassuch as nitrogen gas 540 is introduced into the titanium nitridedeposition chamber 505. Also shown in each of the deposition chambers500,505 is a wafer 510 supported on a chuck 520. Not shown in any of thefigures are means for introducing argon gas into the chambers 500,505which is used in the sputtering of titanium during the deposition ofboth titanium and titanium nitride.

In the flash titanium deposition chamber 500 the flash titanium layer120 is deposited onto the surface of the wafer 510, whereas in thetitanium nitride deposition chamber 505 the antireflective layer 130 isdeposited onto the surface of the wafer 510. A given wafer 510 is firstplaced in the flash titanium deposition chamber 500, the titanium target530 sputters flash titanium layer 120 onto the wafer 510, the wafer isremoved from the flash titanium deposition chamber 500 and placed in thetitanium nitride deposition chamber 505, nitrogen gas 540 is introducedinto the titanium nitride deposition chamber 505 via port 550, and thenin the presence of the nitrogen gas 540 the titanium target 530 sputtersthe antireflective layer 130 onto the wafer 510. When the wafer 510 isremoved from the titanium nitride deposition chamber 505, the wafer 510will be in the condition of FIG. 1A. In other words, the wafer 510 willnot have the unintentional titanium nitride layer 140 deposited on it.In this way, the target 530 and walls of the flash titanium depositionchamber 500 are not contaminated with titanium nitride.

FIG. 5C is a flow chart of a method for creating an integrated circuitstructure 100 using the two deposition chambers of FIGS. 5A and 5B. Inblock 1510 of FIG. 5C, the wafer 510 is placed in the flash titaniumdeposition chamber 500 of FIG. 5A. Block 1510 then transfers control toblock 1515.

In block 1515, the flash titanium layer 120 is deposited on top of theinterconnect conductor 110 on the wafer 510 in the flash titaniumdeposition chamber 500. Block 1515 then transfers control to block 1520.

In block 1520, the wafer 510 is removed from the flash titaniumdeposition chamber 500 of FIG. 5A. Block 1520 then transfers control toblock 1525.

In block 1525, the wafer 510 is placed in the titanium nitridedeposition chamber 505 of FIG. 5B. Block 1525 then transfers control toblock 1530.

In block 1530, nitrogen gas 540 is introduced into the titanium nitridedeposition chamber 505 of FIG. 5B. Block 1530 then transfers control toblock 1535.

In block 1535, the antireflective layer 130 is deposited onto the waferin the titanium nitride deposition chamber 505 of FIG. 5B. Block 1535then transfers control to block 1540.

In block 1540, the wafer 510 is removed from the titanium nitridedeposition chamber 505 of FIG. 5B. Block 1540 then terminates theprocess.

In another method, the titanium nitride deposition chamber 505 as shownin FIG. 5B is used for depositing both the flash titanium layer 120 andthe antireflective layer 130. Once a particular wafer 510 has receivedthe deposition of both the flash titanium layer 120 and theantireflective layer 130 and has been removed from the titanium nitridedeposition chamber 505, and before the next wafer 510 is introduced intothe titanium nitride deposition chamber 505, the chamber receives atitanium pasting. During the titanium pasting, the target 530 in thetitanium nitride deposition chamber 505 is cleared of any titaniumnitride residual from the deposition of the antireflective layer 130 onthe previous wafer 510. Also at the same time, any residual titaniumnitride on the walls and other parts of the titanium nitride depositionchamber 505 which would have been caused by the deposition of theantireflective layer 130 on the previous wafer 510 is covered over.Thus, the next incoming wafer 510 experiences the same chamberenvironment as the previous wafer 510.

FIG. 5D is a flow chart of a method for creating an integrated circuitstructure 100 using pasting as described in various representativeembodiments. In block 1550 of FIG. 5D, a wafer 510 is placed in thetitanium nitride deposition chamber 505 as shown in FIG. 5B. Block 1550then transfers control to block 1555.

In block 1555, the flash titanium layer 120 is deposited on top of theinterconnect conductor 110 on the wafer 510 in the titanium nitridedeposition chamber 505. Block 1555 then transfers control to block 1560.

In block 1560, nitrogen gas 540 is introduced into the titanium nitridedeposition chamber 505 of FIG. 5B. Block 1560 then transfers control toblock 1565.

In block 1565, the antireflective layer 130 is deposited into the waferin the titanium nitride deposition chamber 505 of FIG. 5B. Block 1565then transfers control to block 1570.

In block 1570, the wafer 510 is removed from the titanium nitridedeposition chamber 505 of FIG. 5B. Block 1570 then transfers control toblock 1575.

In block 1575, the titanium nitride deposition chamber 505 of FIG. 5B istitanium pasted after introducing dummy wafers onto the chuck 520.Titanium pasting includes sputtering the titanium target typically withargon gas for a significant amount of time, such that all residualtitanium nitride from the target is cleared leaving only the titanium ofthe base target material. Block 1575 then transfers control to block1580.

In block 1580, if there are more wafers 510 to receive the flashtitanium layer 120 and the antireflective layer 130, block 1580transfers control to block 1550. Otherwise, block 1580 terminates theprocess.

FIG. 6A is a drawing of still another deposition chamber as described invarious representative embodiments. In FIG. 6A, a third depositionchamber 605, also referred to herein as a shield deposition chamber 605comprises target 530 which in the representative embodiment of FIG. 6Ais titanium target 530. The shield deposition chamber 605 includes gasport 550 by which nitrogen gas 540 is introduced into the shielddeposition chamber 605. Also shown in the shield deposition chamber 605is the wafer 510 on chuck 520.

Once a new wafer 510 is introduced into the shield deposition chamber605, a shield 640 which is supported by a post 650 is rotated into aposition between the target 530 and the wafer 510 which is situated onthe chuck 520. Any titanium nitride remaining on the target 530 fromprior processing is then sputtered off while the shield 640 protects thewafer from receiving the unintentional titanium nitride layer 140.Following this cleaning of the target 530, the shield 640 is removedfrom between the target 530 and the wafer 510, and the flash titaniumlayer 120 is deposited onto the surface of the wafer 510. And finallynitrogen gas 540 is introduced into the shield deposition chamber 605and sputtering of the titanium target 530 is initiated in order todeposit the antireflective layer 130 onto the surface of the wafer 510.When the wafer 510 is removed from the titanium nitride depositionchamber 505, the wafer 510 will be in the condition of FIG. 1A. In otherwords, the wafer 510 will not have the unintentional titanium nitridelayer 140 deposited on it.

FIG. 6B is a flow chart of a method for creating an integrated circuitstructure 100 using the shield 640 as described in variousrepresentative embodiments. In block 1605 of FIG. 6B, a wafer 510 isplaced in the shield deposition chamber 605 shown in FIG. 6A. Block 1605then transfers control to block 1610.

In block 1610, if the shield 640 covers the wafer 510, block 1610transfers control to block 1620. Otherwise, block 1610 transfers controlto block 1615.

In block 1615, the shield 640 is rotated so as to cover the wafer 510.Block 1615 then transfers control to block 1620.

In block 1620, any titanium nitride on the titanium target 530 isremoved by sputtering. Block 1620 then transfers control to block 1625.

In block 1625, the shield 640 is rotated so as to uncover the wafer 510.Block 1625 then transfers control to block 1630.

In block 1630, the flash titanium layer 120 is deposited on top of theinterconnect conductor 110 on the wafer 510 in the shield depositionchamber 605. Block 1630 then transfers control to block 1635.

In block 1635, nitrogen gas 540 is introduced into the shield depositionchamber 605. Block 1635 then transfers control to block 1640.

In block 1640, the antireflective layer 130 is deposited into the waferin the shield deposition chamber 605. Block 1640 then transfers controlto block 1645.

In block 1645, the wafer 510 is removed from the shield depositionchamber 605. Block 1645 then transfers control to block 1650.

In block 1650, if there are more wafers 510 to receive the flashtitanium layer 120 and the antireflective layer 130, block 1650transfers control to block 1605. Otherwise, block 1650 terminates theprocess.

FIG. 7A is a drawing of a cross-section of even still another integratedcircuit structure 100 as described in various representativeembodiments. In FIG. 7A, the antireflective layer 130 is thinner thanwould otherwise be used and there is no flash titanium layer 120. Theabsence of the flash titanium layer 120 and thinner titanium nitridelayer results in the formation of thicker aluminum nitride regions 720during titanium nitride deposition, as well as subsequent resist ashsteps. However, a thinner antireflective layer 130 enables the contactetch to etch through the titanium nitride of the antireflective layer130, as well as the aluminum nitride region 720 reaching into thealuminum. The aluminum nitride formed is physically sputtered away incontact window 710 which removes any problems with what would otherwisebe the broad contact resistance distribution issue. Low leakage currentcan be obtained by ensuring that the titanium is not free titanium butis in the form of titanium aluminide in contact window 710. In FIG. 7A,the contact window 710, also referred to herein as a contact via 710, isshown as having been etched all the way to the aluminum layer 110.Titanium from the seed titanium layer 230 is then reacted with thealuminum layer 110 to form the titanium aluminide layer 210 duringsubsequent process steps.

FIG. 7A shows the integrated circuit metallization structure 100following disposing of the dielectric layer 220 on top over theantireflective layer 130 and the opening of the contact window 710 inthe opening in the dielectric layer 220 which is shown in FIG. 7A asSiO₂ layer 220. Also, the seed titanium layer 230, the seed titaniumnitride layer 240, and the tungsten plug layer 250 have beensequentially deposited to form an interconnection through the contactwindow 710 or via 710 to the next interconnect layer 100. Prior to theformation of this interconnection, however, the wafer receives atungsten polish. The tungsten polish is again typically a chemicalmechanical polish which removes those parts of the tungsten plug layer250, the seed titanium nitride layer 240, and the seed titanium layer230 that overlie the dielectric layer 220. The integrated circuitstructure 100 is then as shown in FIG. 7A with essentially the onlyremaining tungsten from the tungsten plug layer 250 residing in thecontact window 710. Once again, that remaining part of the tungsten pluglayer 250 is now referred to as the tungsten plug 250.

FIG. 7B is a flow chart of a method for creating an integrated circuitstructure 100 using a thin antireflective coating as described invarious representative embodiments. In block 1705 of FIG. 7B, a wafer510 is placed in the second deposition chamber 505 as shown in FIG. 5B.Block 1705 then transfers control to block 1715.

In block 1715, nitrogen gas 540 is introduced into the second depositionchamber 505 of FIG. 5B. Block 1715 then transfers control to block 1720.

In block 1720, a thin antireflective layer 130 which is typically in therange of 150 to 650 angstroms is deposited onto the wafer in the seconddeposition chamber 505 of FIG. 5B. Block 1720 then transfers control toblock 1725.

In block 1725, the wafer 510 is removed from the second depositionchamber 505 of FIG. 5B. Block 1725 then transfers control to block 1730.

In block 1730, if there are more wafers 510 to receive theantireflective layer 130, block 1730 transfers control to block 1705.Otherwise, block 1730 then transfers control to block 1735.

In block 1735, other processing steps are performed including thecreation of the dielectric layer 220. Block 1735 then transfers controlto block 1740.

In block 1740, a contact via 710 is opened in the dielectric layer 220all the way through the antireflective layer 130 reaching into thealuminum layer 110. Block 1740 then transfers control to block 1745.

In block 1745, the seed titanium layer 230 is deposited. Block 1745 thentransfers control to block 1750.

In block 1750, the seed titanium nitride layer 240 is deposited. Block1750 then transfers control to block 1755.

In block 1755, the tungsten plug 250 is deposited. Block 1755 thentransfers control to block 1760.

In block 1760, the tungsten, titanium nitride, and titanium in regionsother than the tungsten plug regions are removed by using chemicalmechanical polishing in a process typically referred to as a tungstenpolish. Block 1760 then terminates the process.

Tungsten plug deposition, which is generally a chemical vapor deposition(CVD) process, typically occurs at a wafer temperature of 400 DegreesCentigrade or higher. If the wafer temperature is held to less than orequal to 400 degrees centigrade, there will be less hydrogen getteringby the seed titanium layer 230 as compared with a higher temperature oftungsten deposition. During tungsten deposition, the seed titanium layer230 covers all the areas of the wafer and is free titanium. As such, ithas a significant surface area for gettering hydrogen. The lower thetemperature of tungsten deposition, the smaller the amount of hydrogenthat is lost from the silicon/silicon dioxide interface. As previouslystated, this condition enhances the hydrogen passivation of danglingbond defects at the silicon/silicon oxide interface and, thereby,reduces the leakage current. However, a lower tungsten depositiontemperature also reduces the rate of titanium aluminum reaction to formtitanium aluminide. In addition, the lower tungsten depositiontemperature reduces the tungsten deposition rate with associatedresultant lower throughput and increases stress in the wafer. For thesereasons, tungsten deposition temperature cannot be arbitrarily loweredbut is typically held to between 385 and 415 degrees centigrade. Theresulting structure would be as shown in FIG. 2.

It has been found that the leakage current increases above a tungstenplug deposition temperature of 400 degrees centigrade. It is believedthat the dielectric layers on top of the silicon have a significantamount of hydrogen all the way to the silicon surface. As such, if thetemperature is very high, during tungsten plug deposition there will begreater gettering of the hydrogen than otherwise. The diffusion ofhydrogen in oxide and its gettering by titanium are both thermallyactivated processes. As such, the rates for both of these processesincrease significantly with temperature.

During tungsten deposition, titanium on the side-walls of the tungstenplugs 250, as well as on dielectric layer 220 areas, has no aluminum toreact with. As such, these areas act like sources of hydrogen gettering.They take away some of the hydrogen that would otherwise combine withthe dangling bonds at the silicon/silicon dioxide interface. Thiscondition results in a higher leakage current. So, if the temperature oftungsten deposition drops to 400 degrees centigrade or below, the rateof hydrogen diffusion is slower which results in a lower leakagecurrent.

FIG. 8 is a flow chart of a method for creating an integrated circuitstructure 100 using lower temperature tungsten deposition as describedin various representative embodiments. In block 1805 of FIG. 8, a wafer510 is placed in the second deposition chamber 505 as shown in FIG. 5B.Block 1805 then transfers control to block 1815.

In block 1815, nitrogen gas 540 is introduced into the second depositionchamber 505 of FIG. 5B. Block 1815 then transfers control to block 1820.

In block 1820, the antireflective layer 130 is deposited into the waferin the second deposition chamber 505 of FIG. 5B. Block 1820 thentransfers control to block 1825.

In block 1825, the wafer 510 is removed from the second depositionchamber 505 of FIG. 5B. Block 1825 then transfers control to block 1830.

In block 1830, if there are more wafers 510 to receive theantireflective layer 130, block 1830 transfers control to block 1805.Otherwise, block 1830 then transfers control to block 1835.

In block 1835, other processing steps are performed including thecreation of the dielectric layer 220. Block 1835 then transfers controlto block 1840.

In block 1840, a contact via 710 is opened in the dielectric layer 220.Block 1840 then transfers control to block 1845.

In block 1845, the seed titanium layer 230 is deposited. Block 1845 thentransfers control to block 1850.

In block 1850, the seed titanium nitride layer 240 is deposited. Block1850 then transfers control to block 1855.

In block 1855, the tungsten plug 250 is deposited at a depositiontemperature of a lower temperature which is typically between 385 and415 degrees centigrade. Block 1855 then transfers control to block 1860.

In block 1860, the tungsten, titanium nitride, and titanium in regionsother than the tungsten plug regions are removed by using chemicalmechanical polishing in a process typically referred to as a tungstenpolish. Block 1860 then terminates the process.

In summary, representative embodiments of processing methods which canbe integrated into existing integrated circuit processes that usealuminum/tungsten based metallization systems which enable small valuesof leakage currents while controlling the variability of contactresistance and leakage current over large area arrays are disclosedherein.

An antireflective (AR) coating or layer included on top of eachmetallization layer for most advanced integrated circuit processeshaving 0.35 micron or smaller geometries provides a sharper definitionof interconnect pattern. The inclusion of this antireflective coatinghas been found to reduce pattern dispersion during exposure of theinterconnect layer photoresist, thereby producing a sharper resistpattern which results in the sharper interconnect pattern. Typically forthese aluminum/tungsten based metallization systems, a flash titaniumlayer is applied between the aluminum and the antireflective layer whichis generally titanium nitride. Tungsten is used to interconnect thelayers of aluminum interconnection. It has also been found that theflash titanium layer generally prevents a broad distribution of contactresistance which would otherwise result by the formation of aluminumnitride during the deposition of the top antireflective titanium nitrideand subsequent exposure of the wafer to nitrogen plasma during resistash steps.

In order to reduce leakage current, it is important that the titanium beconsumed by the underlying layer of aluminum in forming titaniumaluminide. As the consumption of the titanium by the aluminum isinhibited by the unintentional titanium nitride layer, it is importantto eliminate or reduce the effect of this unintentional titanium nitridelayer. Representative embodiments disclosed herein provide suchtechniques.

The representative embodiments, which have been described in detailherein, have been presented by way of example and not by way oflimitation. It will be understood by those skilled in the art thatvarious changes may be made in the form and details of the describedembodiments resulting in equivalent embodiments that remain within thescope of the appended claims.

1. A method for fabricating a low leakage integrated circuit structure,comprising: disposing an antireflective layer without intervening layersdirectly onto the top of an interconnect conductor, wherein theinterconnect conductor comprises aluminum, wherein the antireflectivelayer comprises titanium nitride, and wherein the antireflective layerhas thickness less than or equal to 650 angstroms and greater than orequal to 150 angstroms; disposing a dielectric layer over theantireflective layer; and opening a contact window, wherein the contactwindow extends at least down to the antireflective layer.
 2. The methodas recited in claim 1, following the step opening the contact window,the steps further comprising: disposing a seed titanium layer over thedielectric layer, wherein the seed titanium layer makes contact with theinterconnect conductor through the contact window; disposing a seedtitanium nitride layer over the seed titanium layer, wherein the seedtitanium nitride layer makes contact with the seed titanium layerthrough the contact window; disposing a tungsten plug layer over theseed titanium nitride layer, wherein the tungsten plug layer makescontact with the seed titanium nitride layer through the contact window;and performing a tungsten polish, wherein the tungsten polish removesthose parts of the seed titanium layer, the seed titanium nitride layer,and the tungsten plug layer overlying the dielectric layer.
 3. Themethod as recited in claim 1, wherein the interconnect conductor isunderlying interconnect layer and wherein the contact window does notextend through the antireflective layer.
 4. The method as recited inclaim 3, wherein the step disposing the antireflective layer comprisesintroducing nitrogen gas into a deposition chamber and sputtering atitanium target in the deposition chamber.
 5. The method as recited inclaim 1, wherein the contact window extends through any aluminum nitrideregion formed during disposition of the antireflective layer and othersteps prior to opening the contact window.
 6. The method as recited inclaim 5, wherein the step disposing the antireflective layer comprisesintroducing nitrogen gas into a deposition chamber and sputtering atitanium target in the deposition chamber.
 7. The method as recited inclaim 5, wherein the dielectric layer comprises silicon dioxide.
 8. Themethod as recited in claim 2, wherein temperature of the integratedcircuit structure during disposing of the tungsten plug is greater thanor equal to 385 degrees centigrade and is less than or equal to 415degrees centigrade.
 9. The method as recited in claim 8, wherein thestep disposing the antireflective layer comprises introducing nitrogengas into a deposition chamber and sputtering a titanium target in thedeposition chamber.
 10. The method as recited in claim 8, wherein theinterconnect conductor comprises aluminum.
 11. The method as recited inclaim 8, wherein the dielectric layer comprises silicon dioxide.
 12. Anintegrated circuit structure, comprising: an interconnect conductordisposed over other integrated circuit structure, wherein theinterconnect conductor comprises aluminum; an antireflective layerdisposed without intervening layers directly onto the top of theinterconnect conductor, wherein the antireflective layer comprisestitanium nitride and wherein the antireflective layer has thickness lessthan or equal to 650 angstroms and greater than or equal to 150angstroms; and a dielectric layer disposed over the antireflectivelayer, wherein the dielectric layer comprises a contact window andwherein the contact window extends at least down to the antireflectivelayer.
 13. The integrated circuit structure as recited in claim 12,further comprising: a seed titanium layer disposed within the contactwindow; a seed titanium nitride layer disposed over the seed titaniumlayer in the contact window; and a tungsten plug disposed over the seedtitanium nitride layer in the contact window.
 14. The integrated circuitstructure as recited in claim 12, wherein the contact window does notextend through the antireflective layer.
 15. The integrated circuitstructure as recited in claim 14, wherein the dielectric layer comprisessilicon dioxide.
 16. The integrated circuit structure as recited inclaim 13, wherein the contact window does not extend through theantireflective layer.
 17. The integrated circuit structure as recited inclaim 16, wherein the dielectric layer comprises silicon dioxide. 18.The integrated circuit structure as recited in claim 12, wherein thecontact window extends through the antireflective layer and any aluminumnitride regions formed during disposition of the antireflective layerand prior to opening the contact window.
 19. The integrated circuitstructure as recited in claim 18, wherein the dielectric layer comprisessilicon dioxide.
 20. The integrated circuit structure as recited inclaim 12, wherein the contact window extends through the antireflectivelayer and any aluminum nitride regions formed during disposition of theantireflective layer and prior to opening the contact window.
 21. Theintegrated circuit structure as recited in claim 20, wherein thedielectric layer comprises silicon dioxide.
 22. A method for fabricatinga low leakage integrated circuit structure, comprising: placing theintegrated circuit structure in a deposition chamber, wherein theintegrated circuit structure has an interconnect conductor disposedthereon and wherein the interconnect conductor comprises aluminum;disposing a flash titanium layer without intervening layers directlyonto the top of the interconnect conductor; disposing an antireflectivelayer over the flash titanium layer, wherein the antireflective layercomprises titanium nitride; and repeating the above steps for at leastone additional integrated circuit structure.
 23. The method as recitedin claim 22, further comprising: following the step disposing the flashtitanium layer directly onto the top of the interconnect conductor:removing the integrated circuit structure from the deposition chamber,wherein the deposition chamber is first deposition chamber and placingthe integrated circuit structure in a second deposition chamber.
 24. Themethod as recited in claim 23, wherein the step disposing the flashtitanium layer directly onto the interconnect conductor comprisessputtering a titanium target in the first deposition chamber and whereinthe step disposing the antireflective layer over the flash titaniumlayer comprises introducing nitrogen gas into the second depositionchamber and sputtering another titanium target in the second depositionchamber.
 25. The method as recited in claim 22, wherein the stepdisposing the flash titanium layer directly onto the top of theinterconnect conductor comprises sputtering a titanium target and priorto the step disposing the antireflective layer over the flash titaniumlayer, further comprising: introducing nitrogen gas into the depositionchamber, wherein disposing the antireflective layer comprises sputteringthe titanium target and wherein the antireflective layer comprisestitanium nitride; removing the integrated circuit structure from thedeposition chamber; and titanium pasting the deposition chamber.
 26. Themethod as recited in claim 22, prior to the step disposing theantireflective layer over the flash titanium layer, the steps furthercomprising: if a wafer in the deposition chamber is not covered by ashield, moving the shield so as to cover the wafer; cleaning the target;and moving the shield so as to uncover the wafer.
 27. The method asrecited in claim 26, wherein the target comprises titanium.
 28. Themethod as recited in claim 27, wherein the step disposing the flashtitanium layer over the interconnect conductor comprises sputtering thetitanium target in the deposition chamber and wherein the step disposingthe antireflective layer over the flash titanium layer comprisesintroducing nitrogen gas into the deposition chamber and sputtering thetitanium target in the deposition chamber.